There is known a dynamic RAM (random access memory) of a type which has reserve word lines or bit lines (also called data lines or digit lines) to compensate for defective bit lines or data lines. For example, Japanese Patent Laid-Open No. 214699/1991 discloses a defect relief technique in the above type of dynamic RAM.
Conventional dynamic RAMs have a problem that a defect is not necessarily relieved even if, for instance, a defective word line is replaced with a reserve word line. To solve this problem, it may be conceivable to perform defect relief by testing reserve word lines to determine whether they are defective or not. However, to determine whether reserve word lines are defective or not, it is necessary to establish a test mode that is different from an ordinary operation and then perform a test by accessing memory cells that are connected to reserve word lines or bit lines. Therefore, its procedure and test pattern generation are different than the case of a usual test pattern. For this reason, in mass-production of dynamic RAMs, which requires shortening of a test period, it is presently difficult to test every reserve word line or bit line.
In conventional dynamic RAMs, reserve word lines or bit lines are provided in an end portion of a memory mat. In accordance with the present invention, it was intended to increase a substantial defect relief probability paying attention to the fact that the rate of defect occurrence is higher in an end portion of a memory mat than in its central portion. Furthermore, in accordance with the present invention, a problem was found in that in a dynamic RAM having twisted bit lines in a central portion to reduce influences of capacitance coupling between adjacent bit lines, if reserve word lines are provided in an end portion of a memory mat, unbalance occurs in the numbers of crossing word lines, resulting in unbalanced bit line capacitances.
An object of the present invention is to provide a semiconductor memory device which can increase a defect relief probability.
Another object of the invention is to provide a semiconductor memory having an improved operational margin.
The above and other objects and novel features of the invention will become apparent from the description of this specification and the accompanying drawings.